1. Field of the Invention
The present invention relates to a CMOS static memory and, more particularly, to a CMOS static memory in which the constituent elements of a memory cell are arranged point symmetrical.
2. Description of the Prior Art
A full CMOS static random access memory (to be abbreviated as an SRAM hereinafter) disclosed in Japanese Unexamined Patent Publication No. 3-114256 is known as a conventional CMOS static memory in which two driver transistors, two load transistors, and two switching transistors in a memory cell are respectively arranged point symmetrical. The arrangement will be described below with reference to FIGS. 1 to 3.
FIG. 1 is a circuit diagram of a full CMOS SRAM cell. An SRAM cell is located at an intersection between complementary data lines DL1 and DL2 and a set of word lines WL1 and WL2 and connected to the data and word lines by switching transistors Qt1 and Qt2. The source regions of driver transistors Qd1 and Qd2 are connected to a ground wiring Vss, and the source regions of load transistors Q11 and Q12 are connected to a power supply wiring Vcc. The switching transistors Qt1 and Qt2 and the driver transistors Qd1 and Qd2 are n-channel MOSFETs while the load transistors Q11 and Q12 are p-channel MOSFETs.
FIG. 2 is a plan view showing the layout of the unit cell of the full CMOS SRAM. FIG. 3 is a plan view schematically showing the main part of the unit cell in FIG. 2, and FIG. 4 is a perspective view showing a section taken along a line A-B in FIG. 2.
The switching transistor Qt1 is constituted by source and drain regions 117 and 118 and a gate electrode 111. The switching transistor Qt2 is constituted by source and drain regions 127 and 128 and a gate electrode 116. The driver transistor Qd1 is constituted by source and drain regions 120 and 119 and a gate electrode 112. The driver transistor Qd2 is constituted by source and drain regions 125 and 126 and a gate electrode 115. The load transistor Q11 is constituted by source and drain regions 123 and 124 and a gate electrode 114. The load transistor Q12 is constituted by source and drain regions 122 and 121 and a gate electrode 113. Source connecting electrodes 139 and 140 of the driver transistor Qd1 and Qd2 serve as ground wiring layers. A source connecting electrode 147 of the load transistors Q11 and Q12 serves as a power supply wiring. A connection wiring 137 is connected to the gate electrode of the driver transistor Q11, the drain region of the load transistor Q12, the gate electrode of the load transistor Q11, and the drain region of the driver transistor Qd2 through contact holes 130, 131, 133, and 136, respectively. A connection wiring 138 is connected to the drain region of the driver transistor Qd1, the gate electrode of the load transistor Q12, the drain region of the load transistor Q11, and the gate electrode of the driver transistor Qd2 through contact holes 129, 132, 134, and 135, respectively.
This cell arrangement has the following features.
(1) The source and drain regions 119, 120, 126, and 125 and the gate electrodes 112 and 115 of the two driver transistors Qd1 and Qd2, the source and drain regions 123, 124, 122, and 121 and the gate electrodes 114 and 113 of the two load transistors Q11 and Q12, the source and drain regions 117, 118, 128, and 127 and the gate electrodes 111 and 116 of the two switching transistors Qt1 and Qt2, and the connection wiring 137 and 138 for connecting the gate electrodes and the source and drain regions are arranged symmetrical about a central point C of the cell.
(2) All the gate electrodes 111 to 116 of the MOSFETs are arranged in parallel.
(3) The source and drain connecting electrodes 139 to 147 of the MOSFETs are formed by self-alignment using a field insulating film as a mask.
Because of feature (1), the structures of portions where a memory node capacitance is formed in the cell are arranged symmetrical, so that the storage capacitances are equalized with each other to stabilize the storage state. Because of features (2) and (3), the sizes of the source and drain regions in a direction perpendicular to the gate electrodes are reduced to arrange the MOSFETs close to each other, thereby improving the degree of integration.
In this conventional CMOS static memory, the ground and power supply wiring are formed by the source region extraction electrodes between the gate electrodes which are arranged in parallel, so that the wiring width is limited by an interval between the gate electrodes. For this reason, the wiring resistance increases with an advance in micropatterning. This causes increase in ground potential and decrease in power supply potential, which are supplied to the cell, thereby degrading the stability of the cell. Although a conductive layer serving as a ground wiring and a power supply wiring can be formed with a sufficient wiring width on the connection wiring, this increases the number of steps in formation of the wiring and the contact holes. Additionally, since the gate electrodes and the drain regions are connected by the connection wiring, nine contact holes including contact holes (1/2.times.2) for the data lines need to be formed in the unit cell. Therefore, micropatterning of the cell is undesirably limited due to a margin around a contact hole, which is required to ensure a contact hole yield, i.e., a cell yield. Particularly, in connection of the connection wiring and the gate electrodes, the contact holes are formed in the entire source regions due to misalignment of contact holes on the gate electrodes, thereby causing a short circuit between the contact holes and the gate electrodes. For this reason, a sufficient margin is required between the contact hole and the gate electrode.